Constant voltage generating circuit for selectively generating a constant voltage at a high-speed

ABSTRACT

A constant voltage generating circuit for controllably generating a constant voltage at a high speed in response to a control signal and operable with a small power consumption is disclosed. The constant voltage generating circuit comprises first and second output field effect transistors connected in series between first and second voltage terminals, a bias circuit having a series circuit of impedance elements and at least one switch element connected in series between the first and second voltage terminals, first and second intermediate nodes of the series circuit being connected to the gates of the first and second transistors respectively, the switch element taking a conductive state in response to a first level of the control signal a non-conductive state in response to a second level of the control signal, first and second capacitors, a first control circuit for charging the first and second capaitors in response to the second level of the control signal, and a second control circuit for applying electric charges stored in the first and second capacitors to the first and second intermediate nodes in response to the first level of the control signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a constant voltage generating circuitfor selectively generating a constant voltage, and more particularly toa constant voltage generating circuit for quickly generating a constantvoltage upon request thereof.

2. Description of the Related Art

Constant voltage generating circuits have been widely used forgenerating constant voltages which are usually utilized as a referencevoltages in various fields. For example, in a dynamic memory device, aconstant voltage generating circuit is employed for generating areference voltage used for precharging bit lines. Namely, in a dynamicmemory device employing a one-transistor type memory cell, each pair ofbit lines are precharged to a reference voltage having an intermediatelevel of the logic "1" and "0" levels prior to a read operation. Aread-out signal from a selected memory cell is applied to one of a pairof bit lines to compare its potential with the reference voltageprecharged to the other bit line of the same pair for determining alogic level of the read-out signal. Since the constant voltage generatedby the generating circuit is not continuously utilized but is used foronly a predetermined period. Therefore, such a constant voltagegenerating circuit that produces a constant voltage in a controlledmanner when the output of the constant voltage is necessary.

A conventional constant voltage circuit of this type is constructed byan output series circuit having a first field effect transistorconnected between a first voltage terminal and an output terminal and asecond field effect transistor connected between the output terminal anda second voltage terminal and a control circuit for rendering the firstand second transistors conductive thereby to produce a constant voltageat the output terminal in a first mode and non-conductive to set theoutput terminal at a high impedance state in a second mode. The controlcircuit includes resistors, field effect transistors and switch elementsconnected in series between the first an second voltage terminals. Theswitch elements are made conductive in the first mode so that a DCcurrent flows through the control circuit to bias the gates of the firstand second transistors, while the switch elements are madenon-conductive in the second mode to disenable the bias circuit so thatthe gates of the first and second transistors are set at inactivelevels. When the constant voltage generating circuit switched from thesecond mode to the first mode, the gates of the first and secondtransistors are charged to their predetermined bias voltages through theresistors of the control circuit. However, in order to reduce a powerconsumption due to a current flowing through the bias circuit, thevalues of the resistors of the control circuit are made large. Itrequires a relatively large time to precharge the gates of the first andsecond transistors after the transistion from the second mode to thefirst mode. Accordingly, the conventional constant voltage generatingcircuit has a long response time to generate the constant voltage.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a constant voltagegenerating circuit which can produce a constant voltage output at a highspeed upon request therefor.

It is another object of the present invention to provide a constantvoltage generating circuit operable with a low power consumption.

The constant voltage generating circuit according to the presentinvention comprises first and second voltage terminals receiving firstand second voltages, respectively; an output terminal; a first fieldeffect transistor having a source-drain path connected between the firstvoltage terminal and the output terminal and a gate coupled to a firstnode; a first series circuit having a first resistor and a first switchelement connected in series between the first voltage terminal and thefirst node; an impedance circuit coupled between the first node and thesecond voltage terminal; means for receiving a control signal assumingone of first and second levels, a first control circuit coupled to thefirst switch element for rendering the first switch element conductivethereby to generate a first bias voltage at the first node by causing acurrent flowing through the first series circuit and the impedancecircuit in response to the first level of the control signal andnon-conductive in response to the second level of the control signal,the first transistor being rendered conductive in response to the firstbias voltage at the first node thereby to generate a constant voltage atthe output terminal; a second control circuit coupled to the first nodefor operatively setting the first node at a second bias voltage inresponse to the second level of the control signal, the first transistorbeing rendered non-conductive i response to the second bias voltage atthe first node; first and second capacitors each having first and secondends; means for connecting the second end of the first capacitor to oneof the first and second voltage terminals; means for connecting thesecond end of the second capacitor to one of the first and secondvoltage terminals; a first charge circuit coupled to the first capacitorfor operatively charging the first end of the first capacitor to thesecond voltage in response to the second level of the control signal; asecond charge circuit coupled to the second capacitor for operativelycharging the first end of the second capacitor to the first voltage inresponse to the second level of the control signal; a first chargecontrol circuit for operatively short-circuiting the first ends of thefirst and second capacitors thereby to generate a first equilibriumvoltage having a value close to the first bias voltage in response tothe first level of the control signal; and means for applying the firstequilibrium voltage to the first node.

According to the present invention, the first and second capacitors arecharged during a stand-by period when the control signal is at the lowlevel and the equilibrium voltage having the value close to the firstbias voltage is generated by short-circuiting the first and secondcapacitor and applied to the first node as soon as the generatingcircuit is enabled in response to the first level of the control signal.Accordingly, the first node can be set at the first bias voltage at ahigh speed by way of the first and second capacitors in response to thefirst level of the control signal, even though the value of the firstresistor is large.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and further objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription taken in conjunction with the accompanying drawings,wherein:

FIG. 1 is a schematic circuit diagram showing a constant voltagegenerating circuit in the prior art;

FIG. 2 is a timing chart showing the operation of the circuit of FIG. 1;

FIG. 3 is a schematic circuit diagram showing a constant voltagegenerating circuit according to one embodiment of the present invention;

FIG. 4 is a timing chart showing the operation of the circuit of FIG. 3;

FIG. 5 is a schematic circuit diagram of a constant voltage generatingcircuit according to another embodiment of the present invention; and

FIG. 6 is a timing chart showing the operation of the circuit of FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIGS. 1 and 2, the constant voltage generating circuitin the prior art will be explained below.

The constant voltage generating circuit 10 comprises an output stagehaving an N-channel MOS transistor (NMOST) Q₁ and a P-channel MOStransistor (PMOST) Q₂ connected in series between a power voltageterminal Vcc and a ground voltage terminal (GND), and a bias circuitincluding a series circuit of a resistor R₁, a PMOST Q₅, a NMOST Q₃, aPMOST Q₄, an NMOST Q₆ and a resistor R₂ connected in series between Vccand GND and a control circuit having an inverter IV₁ receiving a requestsignal φ₀ generated from an utilization circuit 12 using the constantvoltage output N₁ through an output line 11, a reset NMOS Q₇ and a resetPMOST Q₈. The utilization circuit 12 generates a low (L) level of therequest signal φ₀ when it requests the circuit 10 to output the constantvoltage output V₁, and a high (H) level of φ₀ otherwise.

Operation of the circuit of FIG. 1 will be described in conjunction withthe waveform diagram of FIG. 2. First, so far as φ₀ stays at the L levelduring an active period TA, the PMOST Q₅ and the NMOST Q₆ are renderedconductive, whereby a predetermined current flows through the seriescircuit from Vcc--the resistor R₁ --PMOST Q₅ --NMOST Q₃ --PMOST Q₄--NMOST Q₆ --the resistor R₂ --GND, and predetermined potentials areapplied to connection points N₁₁ and N₂₁. Here, the resistors R₁ and R₂having high resistances are inserted to decrease the current consumed bythe series circuit at the time when the constant voltage is suppliedfrom the connection point N₁ to the circuit 12 that uses the constantvoltage. If the levels at the connection points N₁₁ and N₂₁ are denotedby V₁₁ and V₂₁, then the following equation holds:

    (V.sub.cc -V.sub.11)/R.sub.1 =V.sub.21 /R.sub.2

Further, if the level of the output node N₁ is denoted by V₁, then thereholds the following relation,

    V.sub.1 =V.sub.11 -V.sub.TN =V.sub.21 +V.sub.TP

where V_(TN) and V_(TP) denote threshold voltages of the NMOST Q₃ andthe PMOST Q₄.

From the above equation, the potential V₁ at the connection point N₁ isgiven by the following relation,

    V.sub.1 =(R.sub.2 ·V.sub.cc +R.sub.1 ·V.sub.TP -R.sub.2 V.sub.TN)/(R.sub.1 +R.sub.2)

The circuit 10 supplies this potential as the constant voltage to thecircuit 12.

Next, when the signal φ₀ assumes the H level during a reset periodT_(R), the NMOST Q₇ and the PMOST Q₈ are rendered conductive, while thePMOST Q₅ and the NMOST Q₆ are rendered nonconductive. Thus, theconnecting point N₁₁ assumes ground level and the connection point N₂₁assumes the power sourve Vcc level. Then, the NMOST Q₁ and the PMOST Q₂are rendered nonconductive, and the connection point N₁ set at the highimpedance state (floating condition). Under this condition, therefore,no current is consumed by the circuit 10.

When the signal φ₀ assumes the L level again, the PMOST Q₅ is renderedconductive, and a current is supplied from Vcc via the resistor R₁, tothe connection point N₁₁ that is assuming the ground level. Therefore,the potential rises at the connection point N₁₁. Similarly, the NMOST Q₆is rendered conductive, and the level at the point N₂₁ drops down to theground potential via the resistor R₂. After a predetermined period T_(d)of time has passed, the aforementioned levels V₁₁ and V₂₁ are assumed,and the intermediate level V₁ is supplied to the circuit 12.

In the above-mentioned conventional constant voltage generating circuit,the connection points N₁₁ and N₂₁ are charged and discharged viaresistances of R₁ and R₂ when the reset non-feeding condition ofconstant voltage is to be shifted to the enabled, feeding condition, andthe steady condition is assumed. However, since the resistances of R₁and R₂ are large to reduce the electric power consumed in the circuit10, an extended period of time (T_(d)) is required before the potentialsat the connection points N₁₁ and N₂₁ are stabilized and the output V₁becomes unstable during this period T_(d). Therefore, the conventionalcircuit cannot quickly meet the request for obtaining the constantvoltage.

With reference to FIGS. 3 and 4, the constant voltage generating circuitaccording to one embodiment will be explained.

In FIG. 3, the elements or portions corresponding to those in FIG. 1 aredenoted by the same or similar references and detailed explanationthereof will be omitted.

The constant voltage generating circuit according to this embodiment isfeatured by a charge control circuit 20 in addition to the conventionalcircuit portion 10. The charge control circuit 20 includes capacitorsC₁, C₂, C₃, C₄, NMOSTs Q₉, Q₁₀, Q₁₁, a PMOST Q₁₁, and inverters IV₂ andIV₃.

With reference to FIG. 4, the operation of the circuit of FIG. 3 will beexplained.

During a first active period TA₁ prior to a time point t₁, the requestfrom the utilization circuit 12 assumes the active, L level and itsinverted signal φ₀ ' by the inverter IV₂ is at the H level. Therefore,the NMOSTs Q₉ and Q₁₀ are rendered conductive and the PMOST Q₁₁ and theNMOST Q₁₂ are rendered nonconductive. Thus, the connection points N₁₁and N₂₂ assume a potential equal to V₁₂ and the connection points N₂₁and N₂₂ assume a potential equal to V₂₂.

Next, during a reset period T_(R) from t₁ to t₂ when φ₀ has the H level,and the NMOS Q₁ and PMOST Q₂ are nonconductive to set N₁ at the highimpedance state (Hi-z). Also, the signal φ₀ ' assumes the L level andthe NMOSTs Q₉ and Q₁₀ are rendered non-conductive, so that theconnection points N₁₁ and N₁₂ and the connection points N₂₁ and N₂₂ areisolated from each other. At this moment, as described with reference tothe prior art, the NMOST Q₇ and the PMOST Q₈ are rendered conductive sothat the connection point N₁₁ assumes the ground level and theconnection point N₂₁ assumes the Vcc level. The PMOST Q₁₁ and NMOST Q₁₂are rendered conductive, too, and the connection point N₁₂ assumes theVcc level and the connection point N₂₂ assumes the ground level. Here,if the amounts of electric charges stored in the capacitors C.sub. 2 andC₃ are denoted by Q₂ and Q₃, and potentials at the consumption pointsN₁₂ and N₂₁ are denoted by V₁₂ and V₂₁, then there hold the followingrelation,

    Q.sub.2 =C.sub.2 ·V.sub.12 =C.sub.2 ·V.sub.cc

    Q.sub.3 =C.sub.3 ·V.sub.21 =C.sub.3 ·V.sub.cc

Next, when the condition is changed to a second active period TA₂ fromt₂ and φ₀ is changed to the L level again, the PMOSTs Q₈, Q₁₁ and theNMOSTs Q₇, Q₁₂ are rendered non-conductive. When the NMOSTs Q₉ and Q₁₀are rendered conductive, the potential at the connection point N₁₁approaches that of the point N₁₂ and the potential at the connectionpoint N₂₁ approaches that of the point N₂₂ as the electric charges movefrom C₂ to C₁ and from C₃ to C₄. At this moment, if a resultantpotential at the nodes N₁₁ and N₁₂ is denoted by V₁₁ ' and a resultantpotential at the nodes N₂₁ and N₂₂ is denoted by V₂₁ ' then thefollowing relations hold true from the law of conservation of electriccharge, i.e.,

    (C.sub.1 +C.sub.2)V.sub.11 '=C.sub.2 V.sub.cc

    (C.sub.3 +C.sub.4)V.sub.21 '=C.sub.3 V.sub.cc

Therefore,

    V.sub.11 '=C.sub.1 V.sub.cc /(C.sub.1 +C.sub.2)

    V.sub.21 '=C.sub.3 V.sub.cc /(C.sub.3 +C.sub.4)

Thus, levels at the connection points N₁₁ and N₁₂ can be determinedinstantaneously depending upon the ratios of capacitances of thecapacitors C₁, C₂ and the capacitors C₃, C₄. By adjusting thecapacitances of C₁ -C₄, therefore, the potentials can be brought to thelevels at the connection points N₁₁ and N₁₂ determined by the ratio ofthe resistances R₁ and R₂. That is, referring to FIG. 4, when therequest signal φ₀ is produced, the potentials at the connection pointsN₁₁ and N₂₁ readily reach their stable points and, accordingly, thepotential at the output N₁ readily arrives at its specified level V₁.

FIG. 5 shows the constant voltage generating circuit according toanother embodiment of the present invention. A charge control circuit 30is formed by smaller number of elements than those of the circuit 20 ofFIG. 3, and is controlled by a control signal φ₁. FIG. 6 illustrateswaveforms of control signals and levels at the internal connectionpoints. The control signal φ₁ is a one-shot signal that is activatedonly when φ₀ changes from H into L during T_(d) '. So far as φ₁ remainsat the L level, an NMOST Q₁₃ remains nonconductive. Therefore, so far asφ₀ remains at the H level during T_(R), terminals of the capacitors C₁', C₂ ' on the side of the connection points N₁₁, N₂₁ assume the groundlevel and the power source level Vcc, respectively. If now, φ₀ changesfrom H to L and φ₁ assumes the H level during T_(d) ' whereby the NMOSTQ₁₃ is rendered conductive to give a level V₁₃ expressed by thefollowing equation to the connection points N₁₁ and N₂₁,

    V.sub.13 =C.sub.2 'V.sub.cc /(C.sub.1 '+C.sub.2 ')

Then, the signal φ₁ readily assumes the L level and the NMOST Q₁₃ isrendered non-conductive.

Thus, the level V₁₃ determined by the ratio of capacitances of thecapacitors C₁ ', C₂ ' reaches the specified levels V₁₁ and V₂₁ throughR₁ and R₂ within a very short period T_(d) ' of time compared with thatof the prior art. This embodiment is advantageous in that the controlcircuit constituted by a decreased number of elements supplies aconstant voltage to the circuit 12 at a high speed.

Though ends on one side of the capacitors were grounded in theabove-mentioned embodiments, they need not necessarily be connected in amanner as described above but may suitably be connected to the powersource terminal V_(cc) in accordance with the present invention.

According to the present invention as described above, capacitors areconnected to connection points to where are connected gates of twotransistors that supply an intermediate level of constant voltage, andcharge and discharge of electric charge to and from the capacitors arecontrolled at a moment when the constant voltage is requested.Therefore, the constant voltage of a stable level can be quicklysupplied to the circuit without increasing the consumption of electricpower by the circuit.

What is claimed is:
 1. A voltage generating circuit comprising first andsecond voltage terminals receiving first and second voltages,respectively; an output terminal; a first field effect transistor havinga source-drain path connected between said first voltage terminal andsaid output terminal and a gate coupled to a first node; a first seriescircuit having a first resistor and a first switch element connected inseries between said first voltage terminal and said first node; meansfor connecting said first node and said second voltage terminal; meansfor receiving a control signal assuming one of first and second levels,a first control circuit coupled to said first switch element forrendering said first switch element conductive thereby to generate afirst bias voltage at said first node by causing a current flowingthrough said first series circuit and said impedance circuit in responseto said first level of said control signal and non-conductive inresponse to said second level of said control signal, said firsttransistor being rendered conductive in response to said first biasvoltage at said first node thereby to generate a constant voltage atsaid output terminal; a second control circuit coupled to said firstnode for operatively setting said first node at a second bias voltage inresponse to said second level of said control signal, said firsttransistor being rendered non-conductive in response to said second biasvoltage at said first node; first and second capacitors each havingfirst and second ends; means for connecting the second end of said firstcapacitor to one of said first and second voltage terminals; means forconnecting the second end of said second capacitor to one of said firstand second voltage terminals; a first charge circuit coupled to saidfirst capacitor for operatively charging the first end of said firstcapacitor to said second voltage in response to said second level ofsaid control signal; a second charge circuit coupled to said secondcapacitor for operatively charging the first end of said secondcapacitor to said first voltage in response to said second level of saidcontrol signal; a first charge control circuit for operativelyshort-circuiting the first ends of said first and second capacitorsthereby to generate a first equilibrium voltage having a value close tosaid first bias voltage in response to said first level of said controlsignal; and means for applying said first equilibrium voltage to saidfirst node.
 2. The voltage generating circuit according to claim 1,further comprising a second field effect transistor having asource-drain path connected between said output terminal and said secondvoltage terminal and a gate connected to a second node.
 3. The constantvoltage generating circuit according to claim 2, in which said impedancecircuit includes a second series circuit of a second resistor and asecond switch element connected in series between said second node andsaid second voltage terminal; a third control circuit for rendering saidsecond switch element conductive thereby to set said second node at athird bias voltage that makes said second transistor conductive inresponse to said first level of said control signal and non-conductivein response to said second level of said control signal; and a fourthcontrol circuit coupled to said second node for operatively setting saidsecond node at a fourth bias voltage that makes said second transistornon-conductive in response to said second level of said control signal.4. The voltage generating circuit according to claim 3, furthercomprising third and fourth capacitors each having first and secondends; means for connecting the second end of said third capacitor to oneof said first and second voltage terminals; means for connecting thesecond end of said fourth capacitor to one of said first and secondvoltage terminal; a third charge control circuit for operativelycharging the first end of said third capacitor to said first voltage inresponse to said second level of said control signal; a fourth chargecontrol circuit for operatively charging the second end of said fourthcapacitor to said second voltage in response to said second level ofsaid control signal; a second charge control circuit for operativelyshort-circuiting the first ends of said third and fourth capacitorsthereby to generate a second equilibrium voltage having a value close tosaid third bias voltage in response to said first level of said controlsignal; and means for applying said second equilibrium voltage to saidsecond node.
 5. A constant voltage generating circuit comprising firstand second voltage terminals for receiving first and second voltages,respectively; an output terminal; a first field effect transistor havinga source-drain path connected between said first voltage terminal andsaid output terminal and a gate connected to a first node; a secondfield effect transistor having a source-drain path connected betweensaid output terminal and said second voltage terminal and a gateconnected to a second node; a first series circuit of a first resistorand a first switch element connected in series between said firstvoltage terminal and said first node; a second series circuit of asecond resistor and a second switch element connected in series betweensaid second node and said second voltage terminal; a impedance circuitconnected between said first and second node; means for receiving acontrol signal assuming one of first and second levels; a first controlcircuit coupled to said first and second switch elements for renderingsaid first and second switch elements conductive thereby to cause acurrent flowing through said first series circuit, said impedancecircuit and said second series circuit as that said first and secondnodes are biased for making said first and second transistors conductivein response to said first level of said control signal, andnon-conductive in response to said second level of said control signal;a second control circuit coupled to said first and second nodes forbiasing said first and second nodes for making said first and secondtransistors non-conductive in response to said second level of saidcontrol signal; first and second capacitors; a first charge circuitcoupled to one end of said first capacitor for charging the one end ofsaid first capacitor to said second voltage in response to said secondlevel of said control signal; a second charge circuit coupled to one endof said capacitor for charging the one end of said second capacitor tosaid first voltage in response to said second level of said controlsignal; and a first charge control circuit coupled to the one ends ofsaid first and second capacitors, said first charge control circuitoperatively generating a first equilibrium voltage by short-circuitingthe one ends of said first and second capacitors in response to saidfirst level of said control signal; and means for applying saidequilibrium voltage to said first node.
 6. The constant voltagegenerating circuit according to claim 5, further comprising third andfourth capacitors; a third charge circuit coupled to one end of saidthird capacitor to charge the one end of said third capacitor to saidsecond voltage in response to said second level of said control signal;a fourth charge circuit coupled to one end of said fourth capacitor tocharge the one end of said fourth capacitor to said first voltage inresponse to said second level of said control signal; a second chargecontrol circuit coupled to the one ends of said third and fourthcapacitors for generating a second equilibrium voltage byshort-circuiting the one ends of said third and fourth capacitors inresponse to said first level of said control; and means for applyingsaid second equilibrium voltage to said second node.
 7. The constantvoltage generating circuit according to claim 5, further comprisingmeans for applying said first equilibrium voltage to said second node.